Is jitter a problem for SDH? How it occurs and what is the mechanism to control it?

I presume that by SDH you mean Synchronous Data Hierarchy. Yes, jitter is a problem. The higher the data rate, the greater is the problem with jitter, which is the variation in the timing from one signal edge to the next.





Reducing jitter basically entails all methods used to ensure signal integrity, including impedance matching of driving output, transmission line and receiver input impedance. Also, board layout is critical in that outgoing and return currents must remain as close to each other as practical at all times and the transmission lines must be kept away from all other signal sources and lines. These guidelines are true of both clock and data lines.





There is much more to it than this. I have given 1 hour seminars on this subject and still not completely covered more than the very basic fundamentals. You really need a good college course to understand this. Unfortunately, many college professors do not understand this area well enough to adequately teach it. However, I hope this information has helped at little.